verification planning

Ensuring trustworthiness across the full lifecycle—design, operation, and evolution—of autonomous systems faces two key challenges: the fragmentation between design-time and run-time assurance, and insufficient adaptability to dynamic environmental and operational changes. This paper proposes a unified continuous assurance framework that integrates formal verification (via RoboChart), probabilistic risk analysis (using PRISM), and assurance case modeling through a model-driven approach, enabling co-modeling and dynamic updating of assurance artifacts. The framework supports automated traceability, reconstruction, and regeneration of assurance arguments, thereby establishing an end-to-end trust chain spanning design, operation, and evolution phases. An Eclipse plugin implements automated model transformation and argument generation. Evaluated on a nuclear inspection robot case study, the framework significantly enhances system trustworthiness, regulatory compliance, and alignment with tripartite AI principles—accountability, transparency, and robustness.

This study addresses the limitations of existing SysML verification approaches, which are often tool-dependent and restricted to performance properties, lacking support for automated validation of behavioral and interface requirements. To overcome these shortcomings, this work proposes a tool-agnostic, automated verification workflow driven by SysML test cases, integrating UML Testing Profile and behavioral diagram constructs to enable unified validation of multidimensional attributes—including behavior, timing, and state responses. The methodology was developed through a mixed-methods research strategy combining literature review and stakeholder interviews, and its efficacy was empirically validated across two independent SysML toolchains. The approach not only transcends the constraints of conventional parametric methods but also enables automatic traceability of verification results back to the original model elements.

In hardware logic verification, conventional dynamic simulation and module-level approaches fail to ensure comprehensive transaction-level functional coverage and suffer from poor verification result reusability. This paper proposes the first transaction-level (TL) hierarchical deductive formal verification framework. It extends the PDVL language to support functional coverage and assertion modeling, compiles PDVL specifications into Coq-verifiable Gallina code, and automates the translation of functional coverage goals into proof obligations. The framework enables cross-layer verification reuse and supports formal verification of SVA assertions. Crucially, achieving 100% functional coverage is formally equivalent to establishing system completeness—a rigorous proof of correctness. Our approach delivers high verification accuracy while significantly improving reusability and efficiency over traditional assertion-based verification (ABV) and simulation hybrid methods.

This work addresses the challenge that current large language models (LLMs) often produce low-quality SystemVerilog assertions with insufficient functional coverage due to a limited understanding of integrated circuit (IC) design semantics. To overcome this, the authors propose CoverAssert, a framework that constructs a lightweight joint embedding by integrating semantic features of assertions with structural features from their abstract syntax trees (ASTs). This embedding enables clustering and subsequent mapping back to functional specifications to evaluate coverage quality. A closed-loop feedback mechanism based on functional coverage is then established to guide the LLM in iteratively refining assertions for uncovered functionality. Experiments on four open-source designs demonstrate that integrating CoverAssert yields average improvements of 9.57%, 9.64%, and 15.69% in branch, statement, and toggle coverage, respectively.

To address low efficiency, insufficient coverage, and poor RTL bug detection in FSM-based chip functional verification, this paper proposes an EDA-feedback-driven, closed-loop LLM testbench generation method. Initial testbenches are generated using GPT-3.5 or GPT-4; then, real-time signal-level feedback—including code and state coverage metrics and error diagnostics—from commercial EDA tools (e.g., Synopsys VCS) is integrated into the prompt engineering process, enabling iterative refinement. This work pioneers deep integration of EDA tool feedback into the LLM generation pipeline, supporting coverage-guided automated test generation and concurrent RTL-level bug detection. Evaluated on multiple industrial-grade FSM designs, the method improves code and state coverage by 20–35% over baseline approaches and successfully identifies timing and control-logic bugs missed by manual verification. The approach significantly enhances both verification efficiency and reliability.

This work addresses the high cost of manually writing formal specifications and the limitations of existing large language model (LLM)-based approaches that require white-box access to source code, thereby posing intellectual property and deployment constraints. The authors propose a black-box-driven method that leverages only test code and dynamic execution traces to generate candidate Java Modeling Language (JML) specifications via an LLM. These candidates are locally validated using bounded model checking, and an iterative feedback loop refines them based on verification outcomes. This approach is the first to enable fully automated formal specification generation without any access to the program’s internal structure. Evaluated on the SpecGenBench benchmark, it demonstrates that test-derived information effectively guides specification synthesis, while also highlighting critical challenges in checker compatibility and diagnostic feedback, substantially enhancing industrial applicability.

This work addresses the limitations of traditional structural coverage metrics in embedded software testing, which are often confined to the unit level and fail to reflect true coverage completeness in integration and system testing. Instrumentation-based approaches risk perturbing runtime behavior, while pure tracing techniques suffer from unreliability under high compiler optimization. To overcome these challenges, the paper proposes an integration-test-driven coverage strategy featuring a novel “integration-first” closed-loop workflow. By synergistically combining embedded tracing with hybrid runtime analysis (hRA) to preserve semantic boundaries, and leveraging source-to-target mapping for evidential traceability alongside Hyper Coverage for cross-variant merging, the approach establishes a unified evidence-integration mechanism. Evaluated on -O3-optimized release binaries, it reliably achieves branch, condition, and MC/DC coverage measurements and precisely identifies source code lines consistently uncovered across all variants, thereby significantly enhancing confidence in the test completeness of embedded systems.

This work addresses the labor-intensive and error-prone process of manually crafting SystemVerilog Assertions (SVA) from specification documents in assertion-based verification (ABV). It presents the first systematic analysis of the key challenges involved in leveraging large language models (LLMs) for automated SVA generation and proposes a principled methodology that ensures high-quality, standardized outputs. By integrating natural language processing with formal verification techniques, the study formulates guiding principles and practical strategies tailored to the generation of reliable and precise assertions. This approach provides both theoretical grounding and a viable pathway toward building efficient, robust automated verification workflows.

This work addresses the limitations of traditional simulation-based approaches in module-level fault analysis, which are often overly conservative and unable to accurately assess functional safety impacts. The authors propose SafeGen, a novel framework that integrates large language models (LLMs) with document-level hyperknowledge graphs (HyperKGs) to automatically extract verifiable specifications from design and safety documentation, generating semantically precise, design-aware functional safety assertions. By mapping gate-level faults to RTL and leveraging formal property verification (FPV), SafeGen enables semantic-level criticality classification for stuck-at and bridging faults, while supporting end-to-end traceable reasoning across specifications, assertions, and faults. Experimental evaluation on a field-oriented control (FOC) platform demonstrates that the generated assertions outperform those from existing LLM-based methods in quality and provide more semantically interpretable criticality assessments.