characterize dram interference

This work addresses a critical reliability challenge in Processing-using-DRAM (PuD) systems, where high-density DRAMs are vulnerable to disturbances from inactive rows and concurrent column accesses, leading to computational errors. Through empirical evaluation on 96 real DDR4 chips, the study identifies and formally names this interference phenomenon “PuDGhost,” demonstrating that it can induce error rates as high as 10% from inactive rows and 48% from concurrent columns. To mitigate PuDGhost, the authors propose a cross-layer co-design combining hardware and layout optimizations, including Synchronized Multi-Row Activation (SiMRA), a column filtering strategy, and dedicated isolation rows. This integrated approach significantly enhances the robustness of PuD computation and lays a foundation for building reliable PuD systems.

This work identifies and systematically characterizes ColumnDisturb—a novel column-level read disturbance phenomenon in DRAM—where sustained activation of a single row induces multi-bit failures across up to 3,072 rows via shared bitlines across sub-arrays, exceeding RowHammer’s spatial impact. Through empirical evaluation on 216 DDR4 and 4 HBM2 commercial chips (spanning three major vendors, multiple technology nodes, and operating conditions), we demonstrate that ColumnDisturb triggers bit flips within standard refresh intervals; in worst cases, the number of affected rows reaches 198× that of conventional retention failures, worsening significantly with technology scaling. Crucially, ColumnDisturb fundamentally undermines existing retention-aware refresh mechanisms, as it manifests independently of cell leakage and cannot be mitigated by conventional timing-based refresh policies. These findings establish a critical foundation for next-generation DRAM reliability modeling and refresh strategy design.

To address computation errors caused by defective columns in Processing-Using-DRAM (PUD), this work proposes a high-precision column-level calibration method. The approach introduces, for the first time, a column-customized bias generation mechanism leveraging DDR4 DRAM’s multi-level charge states; it achieves wide-range, high-resolution fine-grained bias compensation under row-resource constraints via multi-level charge programming and column-wise bias modeling. Crucially, the scheme is fully compatible with standard DDR4 protocols and requires no hardware modifications. Experimental results demonstrate a 55.2% reduction in erroneous columns, a 1.81× increase in usable computing columns, and 1.88× and 1.89× throughput improvements for PUD addition and multiplication, respectively. This is the first work to incorporate multi-level charge control into column-level PUD calibration, significantly enhancing the co-optimization of reliability and computational efficiency.

This work identifies PuDHammer, a novel read-disturb attack in Processing-using-DRAM (PuD) architectures, triggered by multi-row activation—distinct from conventional single-row RowHammer. PuDHammer exacerbates DRAM read disturbance, reducing the number of hammering operations required to induce first-bit flips by up to 158.58× and evading target-row refresh defenses while synergistically amplifying errors with RowHammer. Method: We conduct hardware fault injection and large-scale characterization across 316 real-world DDR4 chips from multiple vendors and process nodes to quantify cross-manufacturer and cross-process sensitivity variations. Contribution/Results: We provide the first systematic empirical foundation for reliability assessment and security design of PuD systems. We propose three hardware–software co-design mitigation strategies; among them, adaptation of the PRAC mechanism incurs an average performance overhead of 48.26%. Our findings expose critical vulnerability vectors in emerging in-memory computing paradigms and establish benchmarks for future secure PuD architecture development.

DRAM read disturbance phenomena (e.g., RowHammer, RowPress) exhibit persistent discrepancies between empirical measurements and device-level simulations—hindering accurate reliability modeling and hardware-level mitigation design. This work presents the first systematic comparison of measured disturbance behavior across 96 commercial DDR4 chips against state-of-the-art device simulations. We identify fundamental contradictions: (i) bit-flip polarity is inverted relative to predictions from mainstream models, and (ii) disturbance susceptibility exhibits strong, previously unmodeled dependence on access patterns. Through error-mechanism-aware access pattern design, cross-layer validation, and controlled experimental characterization, we expose critical limitations in current DRAM reverse-engineering methodologies and device models—specifically, their lack of physical completeness. These findings challenge foundational assumptions in existing reliability modeling frameworks. Our results provide essential empirical evidence for developing more accurate DRAM disturbance models and robust, hardware-implementation-aware countermeasures.

This study addresses a critical oversight in conventional DRAM disturbance error testing: the dependence of read disturbance on prior write patterns, which existing methods neglect, leading to biased reliability assessments. The authors empirically identify and name this effect the “DejaVu phenomenon,” demonstrating that repeatedly writing identical data enhances a row’s resilience to disturbance, whereas writing complementary data exacerbates its vulnerability. Through experiments on commercial DDR4 chips, controlled write patterns, and analysis of Processing-in-Memory (PIM) reliability, they reveal that this behavior stems from insufficient charge recovery and trap-state dynamics within DRAM cells. Their findings show that the DejaVu effect improves ACmin on average and reduces failing bitlines by 32.7% in MAJ-3 operations. However, they also show that current mitigation schemes must lower their activation thresholds to remain effective, incurring a 6.3% performance overhead, thereby necessitating updates to both testing protocols and protection mechanisms.

This work addresses the security threat posed by DRAM read disturbance effects—such as RowHammer and RowPress—which can induce bit flips in non-target rows. While existing device-level models struggle to accurately explain experimental observations, this study systematically investigates three key metrics: bit-flip polarity, count, and activation-count threshold (ACmin). Through a comparative analysis of TCAD simulations and empirical measurements, the authors uncover significant inconsistencies between current models and real-world data, propose a more accurate physical error mechanism, and identify critical parameters governing simulation fidelity. The refined model successfully reproduces RowHammer and RowPress behaviors observed in actual DRAM chips, thereby establishing a solid theoretical foundation for efficient characterization methodologies and robust mitigation strategies.

This study addresses the misuse of the Ramulator 2.0 memory simulator and unsubstantiated criticisms presented in the so-called “Mess paper.” Through systematic reproduction and configuration auditing, we demonstrate that erroneous simulation settings led to significant evaluation biases. We propose four best practices for memory simulator usage and emphasize the importance of collaborating with original tool developers to validate anomalous findings prior to publication. As the first systematic investigation into simulator misuse in high-impact research, this work not only corrects misconceptions about Ramulator 2.0 but also releases all reproduction artifacts publicly, aiming to foster community-wide standards and collaborative verification mechanisms for simulation-based studies.

This work proposes a physical unclonable function based on Simultaneous Multi-Row Activation of DRAM (SiMRA-PUF), which generates highly unique and reproducible device fingerprints without requiring any hardware modifications to commercial off-the-shelf (COTS) DDR4 chips. Experimental evaluation across 112 modern DDR4 devices demonstrates that, under activation configurations ranging from 2 to 32 rows, the intra-device Jaccard similarity ranges from 89.02% to 94.86%, while inter-device similarity remains low at 2.37%–3.98%. Notably, the 2-row activation configuration achieves a 5.75% improvement in evaluation speed over existing DRAM PUFs. This study presents the first practical DRAM-based PUF that simultaneously offers low latency, high reliability, and compatibility with unmodified commodity hardware, making it well-suited for real-world security applications.