remote procedure calls

This work addresses the significant communication bottleneck in multi-GPU training caused by the serial execution of computation and communication. The authors propose a portable runtime mechanism that requires no modifications to vendor libraries or kernels. By dynamically controlling on-chip resource occupancy of compute kernels, elevating the scheduling priority of communication streams, and leveraging shared memory for compute footprint management and cross-GPU resource coordination, the approach effectively enables concurrent execution of computation and collective communication. Evaluated on NVIDIA A40, A100, H100, and AMD MI250X GPUs, the method reduces end-to-end training time by up to 25.5%.

Hardware disaggregation aims to transcend traditional server boundaries and establish a unified resource pool spanning cabinets or racks, yet faces critical challenges in resource pooling and coordinated scheduling, energy-efficiency optimization, and system-level trade-offs. This paper proposes a cross-layer co-optimization framework integrating system architecture design, resource pooling mechanisms, fine-grained scheduling algorithms, and a multi-objective energy-efficiency evaluation model. It systematically reveals the deep impacts of decoupled architectures on application development, hardware configuration, and power/thermal management. Through numerical modeling and quantitative analysis, we first characterize the three-dimensional trade-off among pooling granularity, scheduling overhead, and energy efficiency—filling a key gap in pooling-scheduling co-optimization research. Experiments demonstrate that our architecture improves resource utilization by 32–47%, reduces Power Usage Effectiveness (PUE) by 0.08–0.15, and significantly enhances adaptability to heterogeneous workloads.

The surging computational demands of large language model (LLM) training exceed the capacity of homogeneous clusters from a single vendor, necessitating heterogeneous collaborative training across AMD and NVIDIA GPUs. This work proposes a compatibility-oriented hybrid communication architecture that integrates CPU-mediated forwarding and direct device-to-device connectivity, and introduces an innovative CPU-offloaded peer-to-peer transfer mechanism that enables cross-vendor GPU data exchange without host memory staging for the first time. By leveraging multi-NIC parallel transmission and differentiated communication backend scheduling, the system achieves 98% of the throughput of an NVIDIA-only homogeneous cluster on LLaMA-8B and Qwen2-7B models while preserving training stability and correctness.

This work addresses the inability of GPUs in current high-performance computing (HPC) systems to autonomously initiate cross-node communication, particularly the lack of an efficient, low-overhead GPU-driven communication mechanism on OFI-based interconnects such as Slingshot, alongside inefficient NIC resource reclamation. The authors propose GICC, a runtime system that, for the first time on OFI architectures, enables GPUs to directly trigger NIC operations without host intervention, facilitating fine-grained overlap of computation and communication. GICC also introduces an asynchronous, lock-free, lightweight resource reclamation mechanism. Experimental results demonstrate a 229× reduction in coordination latency and a 25% improvement in weak scaling efficiency on Slingshot; on InfiniBand, it achieves 1.95× lower Put latency compared to NVSHMEM. In an industrial-scale stencil application, GICC attains 42% parallel efficiency, significantly outperforming MPI’s 35.4%.

To address CPU-induced communication bottlenecks in heterogeneous supercomputing, this paper systematically proposes and classifies the “GPU-centric communication” paradigm—fully migrating communication control from the CPU to the GPU to enable zero-CPU-intervention, end-to-end GPU-direct communication. Methodologically, it integrates GPUDirect RDMA, CUDA Graphs, programmable NICs (e.g., BlueField DPUs), and GPU kernel-level communication primitives to construct a GPU-native communication control stack. Key contributions include: (1) the first systematic characterization of hardware requirements—GPU memory coherence, NIC programmability, and kernel-driver support—and software challenges—including synchronization, error handling, and programming model adaptation; and (2) a design blueprint for low-latency, high-throughput, ultra-low-CPU-overhead communication infrastructure tailored for HPC and distributed AI training. (149 words)

This work addresses the inefficiency of static GPU resource allocation in reinforcement learning caused by long-tailed rollout computations. To tackle this, the authors propose a cooperative elastic mechanism that dynamically reuses idle GPU compute and memory resources within serving clusters to execute rollouts, while strictly adhering to online service-level objectives (SLOs). The approach pioneers efficient, elastic sharing between training and inference resources through three key components: an SLO-aware co-serving executor, a cross-cluster sparse weight transfer engine, and an elastic rollout scheduler. Experimental results demonstrate that, across diverse model scales and cluster configurations, the method achieves 1.20–3.31× higher end-to-end training throughput compared to existing baselines.

This work addresses the challenge of maintaining both timeliness and stability in real-time data streams within scientific workflows, which are highly susceptible to hardware failures, network disruptions, and performance fluctuations in complex environments. The authors propose a lightweight, non-intrusive fault-tolerance mechanism that integrates asynchronous, non-blocking checkpointing with a progress-aware dynamic load redistribution strategy. This approach enables efficient fault recovery and resource rebalancing without interrupting ongoing computations. Under fault-free conditions, the method incurs less than 1% runtime overhead, while in high-failure-rate scenarios, it reduces the impact of faults and performance anomalies by up to sixfold, substantially enhancing the resilience and resource utilization of stream processing systems.

This work addresses the technical and behavioral challenges of transitioning from node-exclusive to resource-aware scheduling in production-grade heterogeneous HPC systems, a shift that risks disrupting established scientific workflows. To enable seamless, non-disruptive migration, the authors propose a collaborative operational framework integrating a time-bound compatibility layer, observability-driven feedback mechanisms, and targeted user guidance. Built upon Slurm’s TRES resource model, the approach combines runtime compatibility support, job queue monitoring, and user behavior analysis to preserve workflow continuity while substantially improving scheduling efficiency. Empirical results demonstrate dramatic reductions in median queue wait times—from 277 minutes to under 3 minutes for CPU jobs and from 81 minutes to 3.4 minutes for GPU jobs—alongside high long-term adoption rates among users who embraced the new submission paradigm.

This work addresses critical reliability and safety issues in NCCL plugins, which execute unverified native code and are prone to task crashes, silent state corruption, and downtime during policy updates. The authors propose a userspace eBPF-based runtime mechanism that seamlessly integrates with NCCL’s existing plugin interface, enabling secure, efficient, and composable communication policy execution without modifying NCCL itself. By leveraging static verification at load time, structured cross-plugin shared maps, and atomic hot-reload capabilities, the system guarantees policy safety, composability, and zero-downtime updates. Experimental results on an 8×NVIDIA B300 GPU system demonstrate that the approach incurs only 80–130 nanoseconds of overhead per decision, completely prevents unsafe behaviors observed in testing, and improves AllReduce throughput by up to 27% across message sizes ranging from 4 to 128 MiB.

Existing in-network computing approaches based on NVLink SHARP suffer from inefficient overlap between communication and computation due to mismatches in their memory semantics, leading to suboptimal resource utilization in multi-GPU systems. This work proposes CAIS, the first compute-aware in-network computing framework, which aligns the memory semantics of large language model (LLM) computation kernels with communication through three key innovations: a compute-aware instruction set and microarchitectural extensions, a coalescing-aware thread block coordination mechanism, and a graph-level dataflow optimizer. By breaking away from conventional communication-centric designs, CAIS achieves significant performance gains—accelerating LLM training by 1.38× over the state-of-the-art NVLS-based approach and by 1.61× compared to the T3 baseline without NVLS.