design analog interaction systems

This work addresses the limited expressivity of modern analog hardware, which is constrained by fixed differential equations and lags far behind software-defined generative models. To bridge this gap, the authors propose the Analog Interaction Systems (AIS) framework, which substantially enhances the representational capacity of analog dynamical systems through time-segmented tunable parameters and latent physical states. By integrating a Wasserstein GAN training strategy, AIS enables end-to-end trainable generative modeling without requiring trajectory alignment. This study presents the first systematic quantification of the expressivity gap between analog systems and neural networks and introduces a hardware-compatible mechanism to close it. On MNIST and Fashion-MNIST, the model achieves FID scores of 27.6 and 80.8, respectively—outperforming prior analog generative models by 3–4×—while consuming only 23 microjoules per image, offering two orders of magnitude energy savings over digital counterparts.

This study addresses the modeling complexity and lack of physical interpretability in large-scale RLC ladder circuits, which arise from their vast number of components. Focusing on canonical ladder structures composed of resistors, inductors, and capacitors, the work presents the first systematic derivation of linear time-invariant state-space models for these three circuit types, uncovering the distinctive matrix structures associated with their high-dimensional second-order differential equations. By leveraging state-space theory and numerical simulations, the paper elucidates the intrinsic dynamic characteristics inherent to each configuration. The proposed framework offers an interpretable and scalable approach to modeling complex passive networks, thereby establishing a rigorous theoretical foundation for simplified analysis and systematic design of such circuits.

Traditional SPICE simulation struggles with strongly nonlinear emerging devices (e.g., ferroelectric memory) due to its reliance on time-discretized numerical solvers, inability to analytically compute derivatives, and lack of native support for inverse problems. To address these limitations, we propose NeuroSPICE—the first systematic framework integrating physics-informed neural networks (PINNs) into circuit simulation. NeuroSPICE directly solves differential-algebraic equations (DAEs) in the time domain via residual minimization and automatic differentiation, enabling end-to-end waveform prediction and generating compact, high-fidelity, differentiable analytical surrogate models. Its core innovations include breaking from conventional SPICE paradigms to natively support joint device-circuit modeling, parameter inversion, and real-time design optimization. Experiments demonstrate that NeuroSPICE significantly improves both simulation efficiency and interpretability for nonlinear circuits, establishing a new paradigm for next-generation EDA tools.

Analog circuit topology synthesis faces two key challenges: existing methods rely on imprecise specifications, neglect engineering constraints, and oversimplify design as graph or code generation—divorcing it from real expert decision-making. This paper introduces the first practical, LLM-driven topology synthesis framework: it embeds domain expertise into large language models, leverages a measured SPICE subcircuit library as primitives, and performs end-to-end topology generation via stepwise block selection, interconnection, chain-of-thought guidance, and iterative SPICE-level validation and correction. Key contributions include: (1) the first formalization of authentic analog design workflow as an LLM agent behavior; (2) construction of the first high-quality benchmark comprising 30 measured circuit cases; and (3) introduction of SPICE-native representation and subcircuit-constrained search. Our method achieves 40% success rate on synthetic data and 23% on real-world data—substantially outperforming GPT-4o (3% and 3%, respectively).

Manual sizing of analog/mixed-signal (AMS) circuits suffers from lengthy design cycles and error-proneness, while existing AI-driven approaches are hampered by prohibitive simulation overhead and poor interpretability. This paper introduces the first large language model (LLM)-based multi-agent collaborative framework for AMS circuit sizing, integrating a reasoning-driven workflow, adaptive simulation control, and design-history learning to enable efficient, transparent, and fully automated optimization. LLM agents collaboratively parse circuit topology and specifications, dynamically orchestrate simulation resources, substantially reduce sample complexity, and avoid common design pitfalls. Experiments across circuits of varying complexity demonstrate that our method improves sample efficiency by 2.1–3.8× over Bayesian optimization and conventional reinforcement learning, accelerates convergence by 47%–63%, and ensures full traceability and verifiability of all design decisions.

This work addresses the inefficiency and heavy reliance on expert knowledge in analog circuit design, particularly within the nonlinear, high-dimensional search space where existing large language model (LLM) approaches struggle to jointly handle topology generation and sizing optimization. To overcome these limitations, the authors propose AaLLM, an end-to-end multi-agent framework featuring a Designer–Critic–Evaluator triad that integrates retrieval-augmented generation (RAG) with automated knowledge base construction to directly translate user specifications into complete netlists. The approach significantly enhances both innovation and efficiency: generated circuits achieve figures of merit (FoMs) comparable to or exceeding those of human-designed counterparts—by up to threefold—while reducing SPICE simulation calls by 3–4.5× and accelerating overall runtime by 40×.

Automated generation of complex analog circuit topologies faces significant challenges due to the combinatorial explosion of the search space and severe data scarcity, rendering existing one-shot generation approaches inadequate for simultaneously achieving high accuracy and customization. This work proposes EXPLORE, a novel framework that uniquely integrates test-time structured search with language model decoding. Leveraging a pretrained Transformer to encode topological priors, EXPLORE employs simulator-guided Monte Carlo Tree Search (MCTS) to concentrate computational effort on critical design decisions and introduces a high-confidence token-skipping mechanism to allocate simulation resources efficiently. Evaluated on a six-component benchmark under a stringent 0.01 tolerance, the method substantially improves generation success rates from 12% (one-shot) and 33% (sample-and-filter) to 65%, while reducing mean squared error by over 20% under identical search budgets.

This work addresses the challenge of jointly optimizing circuit topology and component sizing in analog circuit synthesis by adapting the NeuroEvolution of Augmenting Topologies (NEAT) algorithm for the first time in this domain. By redefining genetic representation, tailoring genetic operators, and incorporating wiring constraints alongside speciation strategies, the proposed method effectively preserves population diversity during evolution while ensuring the generation of valid circuits. The approach enables synergistic co-optimization of topology and sizing, yielding circuits that significantly outperform existing benchmarks in terms of both design quality and reliability across synthesis tasks for square, cube, square root, and cube root functions, demonstrating notable innovation and practical utility.

This work addresses the urgent need for efficient solutions to differential and matrix equations in artificial intelligence and scientific computing by transcending the energy-efficiency and speed limitations of conventional digital computation. It pioneers a unified framework that integrates both classes of equations within a modern analog computing paradigm. Leveraging hardware platforms such as analog CMOS circuits and memristor crossbar arrays, the study systematically constructs a computational primitive centered on matrix-vector multiplication, thereby uncovering intrinsic connections among differential equation solvers, matrix equation solvers, and in-memory computing. The research highlights the superior energy efficiency and parallelism offered by memristor arrays while rigorously examining critical challenges including numerical precision and scalability, ultimately establishing analog computing as a promising enabler for next-generation high-performance computing.