circuit model implementation

In analog circuit design, testbench construction remains manual, severely hindering full-flow automation—particularly in reproducing published circuits, where it suffers from low efficiency and poor flexibility. This paper proposes the first end-to-end, large language model (LLM)-based framework for automatic testbench generation, integrating domain-specific knowledge injection, structured information extraction from research papers, simulation strategy reasoning, and Tsinghua Electronic Design (TED) code generation. We curate a specialized training dataset covering three canonical analog circuits: operational amplifiers, bandgap references, and low-dropout regulators. Experimental results demonstrate that our method generates high-accuracy, directly simulatable TED testbench code, significantly accelerating circuit reproduction. Moreover, it establishes a scalable framework and supplies high-quality, domain-enriched knowledge resources to advance automated EDA research.

This work addresses the scarcity of high-quality training data and testbenches that limits large language models in Verilog code generation. To overcome this challenge, the authors propose a multi-agent collaborative framework for automated testbench generation, enabling the construction of fine-tuning datasets with high coverage and reliability. This approach represents the first application of multi-agent systems to hardware description language generation tasks. By leveraging synergistic interactions among specialized agents, the method significantly reduces reliance on extensive training data while achieving performance on par with state-of-the-art techniques on the VerilogEval v2 benchmark, thereby demonstrating a data-efficient pathway for Verilog code synthesis.

The absence of a systematic survey on large language models (LLMs) for Verilog RTL code generation hinders progress in hardware-AI co-design. Method: This paper conducts a cross-domain (software engineering/AI/EDA) analysis of 102 publications—70 peer-reviewed papers and 32 high-quality preprints—using bibliometric analysis, topic modeling, and cross-domain comparison, complemented by evaluation techniques including fine-tuning, prompt engineering, and functional correctness assessment. Contribution/Results: We introduce the first LLM-Verilog research map and a four-dimensional analytical framework addressing key research questions. Core bottlenecks are identified: architectural limitations of LLMs, scarcity of high-quality Verilog training data, and insufficient functional correctness guarantees. Furthermore, we propose a novel three-stage roadmap—“verifiable generation → hardware-aware alignment → EDA toolchain integration”—to guide future development, offering both theoretical foundations and practical pathways for LLM-driven RTL synthesis.

To address error-prone and inefficient manual Verilog coding in IC design, this paper proposes a multi-AI-agent collaborative framework for end-to-end Verilog generation and repair. Methodologically: (1) a graph-planning mechanism leveraging a task-circuit relational graph enhances mapping fidelity from natural-language specifications to RTL; (2) an AST-driven waveform tracing tool—integrated with symbolic execution—enables precise localization and automatic correction of functional bugs; (3) a closed-loop development pipeline unifies syntactic validation, hardware simulation, and dynamic waveform analysis. Evaluated on the VerilogEval-Human v2 benchmark, the framework achieves 94.2% syntactic and functional correctness—surpassing state-of-the-art methods by 33.9 percentage points—demonstrating substantial progress toward semantically correct, formally verifiable hardware design automation.

This study systematically investigates the interplay between language model characteristics and prompt design in Verilog code generation. Through factorial experiments, it evaluates the performance of three model categories—general-purpose, reasoning-enhanced, and domain-specialized—across diverse prompting strategies, including structured output formatting, chain-of-thought reasoning, in-context learning, and genetic-Pareto optimized prompts. The work presents the first empirical mapping of model–prompt interactions for Verilog generation, revealing distinct response patterns across two benchmarks. It delineates the boundaries of general prompt effectiveness and identifies specific model–prompt dependencies, offering actionable and generalizable prompt engineering guidelines to support efficient hardware-software co-design.

This work presents the first systematic evaluation of large language models (LLMs) in board-level circuit schematic design—a task demanding integrated understanding of physical laws and integrated circuit (IC) datasheet knowledge. To this end, we construct a benchmark comprising 300 real-world design tasks and 2,914 IC datasheets, and introduce a dual verification mechanism combining electrical rule checking (static) and SPICE simulation (dynamic). Experimental results show that even the best-performing model achieves only an 8.15% overall pass rate, revealing that while LLMs exhibit preliminary capability in interpreting engineering documentation, they critically lack physical intuition and remain unreliable for complex hardware design. This study establishes the first standardized evaluation framework for AI-driven electronic design automation.

This work addresses the challenge of deploying large language models in engineering domains such as circuit analysis, where conventional approaches struggle to balance reasoning accuracy with computational efficiency and often overlook the hierarchical structure of domain knowledge. The authors propose a prerequisite-aware, performance-oriented model compression strategy that first constructs a directed acyclic graph (DAG) of circuit analysis concepts to explicitly capture inter-concept dependencies, thereby defining a “complexity boundary” for compressed models. Building on this structure, they introduce a dynamic cascaded querying mechanism that adaptively invokes the smallest viable model according to task complexity. Experimental results demonstrate that this approach precisely aligns model capability with task requirements, achieving significant gains in computational efficiency while preserving high reasoning accuracy.

This work proposes the first end-to-end analog integrated circuit (IC) design automation framework powered by large language models (LLMs), addressing the limitations of existing tools that are typically confined to isolated design stages and rely heavily on manual intervention, particularly when handling unstructured inputs such as circuit schematic images. The proposed framework spans the entire design flow—from schematic image understanding and netlist generation to parameter optimization and placement routing—by integrating in-context learning with intent reasoning to achieve high-fidelity image-to-netlist translation. It further introduces self-augmented prompting and context truncation strategies to construct an efficient parameter search agent. Evaluated on 15 circuits of varying complexity, the framework achieves Pass@1 and Pass@5 success rates of 92.9% and 99.9%, respectively, using GPT-5, substantially outperforming current state-of-the-art methods.

Automated generation of complex analog circuit topologies faces significant challenges due to the combinatorial explosion of the search space and severe data scarcity, rendering existing one-shot generation approaches inadequate for simultaneously achieving high accuracy and customization. This work proposes EXPLORE, a novel framework that uniquely integrates test-time structured search with language model decoding. Leveraging a pretrained Transformer to encode topological priors, EXPLORE employs simulator-guided Monte Carlo Tree Search (MCTS) to concentrate computational effort on critical design decisions and introduces a high-confidence token-skipping mechanism to allocate simulation resources efficiently. Evaluated on a six-component benchmark under a stringent 0.01 tolerance, the method substantially improves generation success rates from 12% (one-shot) and 33% (sample-and-filter) to 65%, while reducing mean squared error by over 20% under identical search budgets.