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Designs, implements, and maps phase-locked loop (PLL) equations onto circuit or simulated components to build neuron models realized as PLL-based circuits. Analyzes and validates the resulting hardware or simulation dynamics—such as phase-locking, synchronization, and bursting—against the underlying PLL mathematical models.
Conventional non-bursting neuron models fail to reproduce intrinsic bursting dynamics, hindering biologically plausible and hardware-efficient neuromorphic implementations. Method: We propose “neuronal burst anatomy”—a design methodology grounded in dynamical systems theory—using the $I_{ ext{Na,p}} + I_{ ext{K}} + I_{ ext{K(M)}}$ model as a qualitative reference. It identifies bifurcation types at burst initiation and termination, and leverages fast-subsystem nullclines and bifurcation diagrams to guide circuit synthesis. Contribution/Results: Two minimal MOSFET-based circuits are implemented, autonomously generating biologically realistic bursting patterns—including square-wave and mixed-type bursts—without external modulation. The approach preserves neurobiological plausibility while drastically reducing component count and enhancing behavioral predictability. Experimental validation confirms robust, low-power operation and interpretable dynamics, establishing a new paradigm for energy-efficient, explainable neuromorphic hardware.
Large-scale coupled oscillator networks—such as power grids and neuromorphic systems—face severe computational bottlenecks in simulation due to high arithmetic intensity and hardware inflexibility. To address this, we present a 28 nm reconfigurable on-chip oscillator network chip. Our approach introduces a clustered phase-locked loop (PLL) architecture, with each cluster integrating seven programmable oscillators, co-designed with an embedded RISC-V coprocessor to enable runtime reconfiguration of both network topology and complexity—the first such capability demonstrated in hardware. The chip incorporates custom analog coupling circuits and a brain-inspired on-chip interconnect fabric, and has been silicon-verified for simulations involving hundreds of oscillators. Measurements show two orders-of-magnitude lower power consumption compared to pure digital simulation, significantly improving energy efficiency and adaptability for analog computing and dynamic modeling of critical infrastructure. This work establishes a new paradigm for hardware-accelerated analog computation.
Existing electronic neuron designs struggle to simultaneously achieve low complexity, functional completeness, and mathematical tractability, thereby limiting their applicability in spiking neural networks. This work proposes a novel bursting electronic neuron architecture grounded in phase-locked loop system equations, employing a hybrid design paradigm that prioritizes target dynamics followed by hardware-aware reverse adaptation. By innovatively integrating phenomenological modeling with circuit simplification strategies, the approach circumvents both direct implementation of complex biophysical models and post-hoc equation fitting. The resulting neuron exhibits a compact structure, controllable dynamics, and strong theoretical analyzability while remaining amenable to hardware realization, making it well-suited for efficient modeling of individual neurons and small-scale neural circuits.
To address the limited temporal representation capability of traditional leaky integrate-and-fire (LIF) neurons—hindering time-sensitive computation—this paper proposes a second-order spiking neuron model grounded in damped-driven pendulum dynamics. By leveraging intrinsic nonlinear oscillatory behavior, the model naturally supports phase coding and periodic spiking, thereby significantly enhancing temporal structure modeling. Integrated with spike-timing-dependent plasticity (STDP), it forms multilayer spiking neural networks, implemented and validated via Brian2 simulations. A lightweight deployment strategy tailored for neuromorphic chips is also devised. Compared to LIF neurons, the proposed model achieves superior biological plausibility, reduced energy consumption, and improved performance on sequence processing and symbolic learning tasks—demonstrating enhanced temporal information encoding and processing. This work establishes a novel, temporally aware neuron primitive for neuromorphic computing.
This study addresses the lack of a systematic review of single-compartment spiking neuron models, which has hindered a clear understanding of the trade-offs between biological plausibility and computational efficiency. For the first time, this work provides a unified survey and classification of mainstream single-compartment spiking neuron models, establishing a taxonomy based on membrane potential dynamics, discrete versus continuous simulation approaches, and mechanisms for abstracting biological behaviors. By delineating the strengths, limitations, and representative applications of each model category, this paper offers a coherent theoretical foundation and practical guidance for model selection in neuromorphic computing and brain-inspired modeling.
This work addresses the problem of automatically synthesizing reactive controllers from Linear Temporal Logic (LTL) specifications for safety-critical systems. We propose a novel framework that integrates automata-theoretic techniques, partial state-space exploration, and machine learning–guided search, enhanced with multiple heuristic strategies and optimized using AIGER/Mealy representations. This approach achieves a breakthrough balance between synthesis efficiency and controller compactness. Evaluated on the SYNTCOMP benchmark suite, our method substantially outperforms state-of-the-art tools—including Strix, LtlSynt, and SemML 1.0—by solving more instances faster while maintaining industry-leading solution quality.
本文提出了一种基于T-时间Petri网的生物神经电路描述方法,解决了现有模拟方法在实时性和精度上的限制,并通过三个微电路仿真验证了其有效性。
This study addresses the inherent challenge in hardware design of balancing complexity management with model accuracy. To this end, it proposes an abstraction-centric methodology that associates discretization techniques with pre-clustered elements, such as transistors. By integrating lumped modeling, value discretization, and time discretization, the approach establishes a well-defined hierarchy of abstractions. The primary contribution of this work is a standardized design methodology that enhances productivity by simplifying model complexity and improving simulation efficiency while defining effective constraints. Consequently, this framework significantly strengthens the capacity to manage complex systems in digital design, thereby advancing overall engineering productivity.
该研究通过引入rail接口和clipper算法,利用分支定界法提高了非线性神经反馈系统验证的可扩展性。
This study addresses the lack of verifiable ground truth in neuroscience for evaluating mechanistic models by introducing a whole-brain neuromechanical simulation platform based on larval zebrafish, which provides a transparent and controllable benchmark environment. The work innovatively integrates large language model (LLM)-guided symbolic regression with neural architectural priors to automatically discover predictive and interpretable models of neural mechanisms through tree search. The resulting models significantly outperform conventional baselines, demonstrate strong out-of-distribution generalization, and accurately recapitulate key functional architectures observed in real neural circuits.