fpga prototyping

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

Traditional HDLs operate at a low abstraction level, requiring manual control/scheduling, while existing functional hardware description tools lack automated scheduling and modular reuse. Method: This paper proposes a functional-programming-based high-level synthesis (HLS) framework that integrates Synchronous Dataflow–Actor Programming (SDF-AP) graph modeling with Haskell extensions—Template Haskell, QuasiQuotes, Generalized Algebraic Data Types (GADTs), and type-level programming—to enable end-to-end, automatic generation of hardware circuits from hierarchical functional specifications, including automatic derivation of data and control flows. Contributions/Results: We introduce (i) the first hierarchical pattern specification mechanism; (ii) GADT-based automatic construction of parameterized buffers; and (iii) built-in executable golden models for closed-loop verification. Experiments show that, compared to Vitis HLS, our framework significantly improves transparency in resource scheduling, timing predictability, and expressiveness of parallel architectures, while yielding more interpretable hardware designs and higher verification efficiency.

Existing hardware assertion generation methods suffer from poor scalability to industrial-scale designs, low assertion quality, insufficient functional coverage depth, and limited interpretability. Method: We introduce the first LLM evaluation benchmark for Verilog designs—comprising 100 open-source circuits and formally verified “gold-standard” assertions—and propose a dedicated evaluation framework integrating functional equivalence checking, multi-dimensional quality metrics, and context-example sensitivity analysis. Contribution/Results: This work fills a critical gap in quantitative LLM assessment for hardware verification. Experiments reveal that state-of-the-art LLMs achieve less than 35% assertion correctness overall, though performance improves markedly with increasing context examples. Systematic deficiencies are identified in modeling temporal logic and finite-state machines. Our benchmark, methodology, and empirical findings provide foundational resources and evidence for advancing LLM-driven hardware verification.

To address the lack of explicit temporal semantics and execution-order modeling in functional languages for high-level synthesis (HLS), this paper proposes a novel hardware description methodology integrating the Synchronous Dataflow with Actor Parameters (SDF-AP) model and Template Haskell. It is the first to embed SDF-AP’s production/consumption timing constraints directly into functional specifications, leveraging higher-order function reuse and dataflow patterns to jointly characterize resource allocation and critical-path latency. Built upon the Clash compiler framework, the approach automatically generates VHDL/Verilog code featuring deterministic timing behavior and complete control- and data-path implementations. Experimental evaluation across multiple benchmarks demonstrates stable resource utilization and strict cycle-accurate timing predictability. Compared to Vitis HLS, the method achieves 23–41% average latency reduction and up to 18% lower resource consumption in selected designs.

To address low efficiency, insufficient coverage, and poor RTL bug detection in FSM-based chip functional verification, this paper proposes an EDA-feedback-driven, closed-loop LLM testbench generation method. Initial testbenches are generated using GPT-3.5 or GPT-4; then, real-time signal-level feedback—including code and state coverage metrics and error diagnostics—from commercial EDA tools (e.g., Synopsys VCS) is integrated into the prompt engineering process, enabling iterative refinement. This work pioneers deep integration of EDA tool feedback into the LLM generation pipeline, supporting coverage-guided automated test generation and concurrent RTL-level bug detection. Evaluated on multiple industrial-grade FSM designs, the method improves code and state coverage by 20–35% over baseline approaches and successfully identifies timing and control-logic bugs missed by manual verification. The approach significantly enhances both verification efficiency and reliability.

This study addresses the challenges of semantic alignment and tool integration in automating hardware verification, particularly concerning assertion generation, debugging, and formal reasoning. To overcome these limitations, this work proposes a neuro-symbolic hybrid architecture that leverages large language models (LLMs) as core orchestration components. By integrating prompt engineering, retrieval-augmented generation, agentic workflows, and SAT/SMT solver optimization techniques, the proposed framework establishes semantic consistency as a critical breakthrough for automated verification pipelines. Furthermore, this paper systematically reviews the application paradigms of LLMs across the entire hardware verification workflow and empirically validates the effectiveness of the hybrid architecture. Finally, it provides an in-depth analysis of the limitations inherent in current evaluation methodologies and outlines promising directions for future research in AI-driven electronic design automation.

This study addresses the absence of evaluations for industrial-grade VHDL and repository-level, multi-file generation in existing large language model (LLM) benchmarks by introducing the first large-scale VHDL repository-level benchmark. Encompassing over one hundred open-source libraries with self-verifying testbenches, the proposed benchmark employs structured problem definitions and module stubbing techniques. Coupled with multi-step reasoning strategies such as Reflexion, it systematically evaluates LLM performance across syntax, semantics, and cross-file reasoning. This work bridges a critical gap in hardware description language evaluation by focusing on VHDL, revealing significant limitations of current models in multi-file coordination and hierarchical design comprehension. Ultimately, this research provides the community with an essential evaluation resource for advancing LLM capabilities in complex hardware design tasks.

This work addresses the limitations of existing hardware parser designs, which suffer from excessive complexity, poor reusability, and inadequate support for sophisticated matching and diverse deployment scenarios. To overcome these challenges, the authors propose an open-source tool that enhances pattern-matching capabilities through customizable symbolic tokens—enabling range validation, negation, and comparisons with external ports—and introduces a Parser Intermediate Representation (PIR) to decouple frontend protocol specification from backend implementation. The frontend allows flexible protocol description, while the backend automatically generates FPGA-optimized SystemVerilog code supporting arbitrary bit-width state machines, byte alignment, and cross-cycle field stitching. Experimental results on an Ethernet parser demonstrate up to a 226% increase in operating frequency and a 97% reduction in logic resource usage; furthermore, the hierarchical design achieves up to 8× greater resource efficiency compared to monolithic architectures.

This work addresses the longstanding divide between software and hardware verification, which has been hindered by the absence of a common intermediate representation that would enable direct application of efficient hardware model checking techniques to C programs. To bridge this gap, the paper introduces the Circuit-based Program Verification (CPV) framework, which systematically compiles C programs into sequential circuits, unifying control-flow and data-flow semantics within a single formal model. CPV integrates established hardware model checking algorithms—including Bounded Model Checking (BMC), k-induction, and IC3/PDR—to support both reachability safety and termination verification. Moreover, it automatically translates counterexamples back into human-readable software evidence. Evaluated on a benchmark suite of over 16,000 verification tasks, CPV matches the performance of leading software verifiers and successfully solves instances beyond the reach of existing tools, demonstrating significant complementary strengths.

This work addresses the challenge that existing C program verification tools struggle to leverage mature hardware model checking backends, limiting both algorithmic generality and efficiency. To bridge this gap, the authors propose a systematic encoding of C programs with assertions into transition systems in the standard BTOR2 format: control flow is modeled via a program counter, data and memory are represented using bit-vectors and arrays, and assumptions and assertions are translated into BTOR2 constraints and bad-state properties. This approach constitutes the first effective integration of software verification with hardware model checking, enabling backend reuse across domains. Evaluated on the SV-COMP ReachSafety benchmark, the method correctly solves 263 tasks—101 more than CBMC—with a 75.5% success rate on bit-vector tasks and zero false alarms.