formal equivalence checking

This work addresses the challenge of verifying functional consistency between high-level algorithmic models and their low-level hardware implementations by proposing the first end-to-end equivalence verification framework based on MLIR. The framework employs a unified lowering pipeline to map diverse design sources—including PyTorch, C/C++, Chisel, Verilog, and gate-level netlists—into a common intermediate representation, which is then automatically translated into standard formal formats such as SMT-LIB, BTOR2, or AIGER. This enables automated pairwise equivalence checking across abstraction layers. For the first time, the approach establishes a complete formal verification flow spanning from algorithmic specifications to gate-level netlists, supporting a “shift-left” verification paradigm and demonstrating efficient, scalable cross-hierarchical verification capabilities, particularly for datapath-intensive designs.

Verifying the equivalence of implementations of the same large model across different frameworks is highly challenging due to significant discrepancies in operator decomposition, tensor layouts, and fusion strategies. This work proposes Emerge, a framework that unifies two implementations into a single e-graph representation, infers candidate equivalences guided by runtime values, and automatically synthesizes rewrite rules on demand without manual intervention. By integrating symbolic SMT-based verification with constraint-aware randomized testing, Emerge supports scenarios involving opaque operators. Experimental results demonstrate that Emerge successfully verifies equivalence for correct implementation pairs, detects 10 out of 13 known bugs, and uncovers 8 previously unknown issues confirmed by developers. The automatically generated block-level rewrite rules achieve effectiveness comparable to handcrafted ones.

Automatically translating natural-language specifications into SystemVerilog Assertions (SVAs) faces fundamental challenges—including linguistic ambiguity, specification incompleteness, and absence of RTL semantics. To address these, we propose the first knowledge graph (KG)-based approach that jointly models specification documents and RTL code, featuring a hardware-specific schema and supporting multi-granularity verification context synthesis. Our method deeply integrates the KG throughout the SVA generation pipeline via RTL semantic parsing, domain-specific entity-relation extraction, and LLM prompt enhancement—enabling context-aware assertion generation. Evaluated on four industrial-scale designs, our approach achieves substantial improvements in assertion coverage (+23.6%) and correctness (+31.4%) over state-of-the-art baselines (e.g., AssertLLM), delivering more reliable and interpretable automation for formal verification.

This work addresses the challenge that large language models (LLMs) often generate erroneous RTL code due to ambiguous or misinterpreted specifications, with such errors typically surfacing only during simulation and proving difficult to trace. To mitigate this, the paper proposes VeriRefine, a novel approach that first refines informal specifications into explicit Abstract Signal Transition Functions (ASTFs)—serving as a verifiable prelude to RTL generation. The method incorporates a five-layer auditing mechanism to validate design intent across dimensions including completeness, consistency, and FSM integrity, and enables targeted debugging by tracing simulation failures back to either specification misunderstandings or coding errors. Evaluated on RTLLM v2.0 and VerilogEval-Human v2, VeriRefine achieves functional correctness rates of 94.0% and 98.1%, respectively, substantially enhancing the reliability and synthesizability of LLM-generated RTL.

This work addresses the challenge of efficiently verifying large-scale RTL designs generated by high-level synthesis (HLS), which often overwhelm conventional model checking techniques. The authors propose a novel method that leverages high-level semantic information from HLS to automatically generate guided invariants, which augment assertions to accelerate formal verification. A proof-guided selection mechanism is introduced to iteratively refine and identify an optimal set of assertions. This approach represents the first systematic integration of HLS-level features into automated invariant generation, substantially improving verification efficiency. Experimental results across multiple HLS benchmarks demonstrate an average speedup of 2.23×, with a maximum acceleration of 6.05× compared to baseline methods.

本文提出了一种基于大型语言模型的行为驱动硬件开发流程，通过定义形式验证Gherkin场景来减少自然语言规范的模糊性，提高硬件设计的形式验证效果。

This study addresses the challenges of semantic alignment and tool integration in automating hardware verification, particularly concerning assertion generation, debugging, and formal reasoning. To overcome these limitations, this work proposes a neuro-symbolic hybrid architecture that leverages large language models (LLMs) as core orchestration components. By integrating prompt engineering, retrieval-augmented generation, agentic workflows, and SAT/SMT solver optimization techniques, the proposed framework establishes semantic consistency as a critical breakthrough for automated verification pipelines. Furthermore, this paper systematically reviews the application paradigms of LLMs across the entire hardware verification workflow and empirically validates the effectiveness of the hybrid architecture. Finally, it provides an in-depth analysis of the limitations inherent in current evaluation methodologies and outlines promising directions for future research in AI-driven electronic design automation.

This work addresses the heavy reliance on manual modeling and proof effort in formal verification of SystemVerilog RTL designs by proposing the first fully automated framework for translating RTL to Lean 4. The approach introduces a four-layer hierarchical theorem library encompassing combinational logic, sequential updates, single-cycle behaviors, and reachability/invariant properties. It further integrates an LLM-driven proof loop that automatically generates intermediate lemmas, admitting only those formally verified by the Lean kernel into a reusable lemma pool. Evaluated on six designs, the method successfully produced 403 theorems, of which 287 foundational lemmas were automatically reusable, achieving a reuse rate of 80.2%. This significantly enhances the automation and scalability of formal RTL verification.

本文针对电路图示等价性问题，提出了三个难度递增的基准测试，并使用TPTP和SMT-LIB格式进行了一阶编码，生成了相应的测试实例。

This study addresses the challenges of insufficient test coverage, misleading textual similarity, and non-executable environments in code equivalence determination by proposing the FEAgent framework. This approach integrates typed program graph alignment with differential agent execution, employing branch-aware input generation and double-blind LLM prediction of observable behaviors to produce an evidence ledger with explicit uncertainty, thereby enabling auditable equivalence judgments that effectively bridge the gap between testing and formal verification. Evaluated on EquiBench and SWE-bench, the framework successfully identifies 216 mislabeled benchmark pairs and 94 defective patches, revealing behavioral divergences overlooked by existing unit tests.