logic synthesis

To address key challenges in RTL code optimization—including error-prone manual rewriting, limited capability of traditional compilers in handling complex design constraints, and poor alignment between LLM-generated outputs and user intent—this paper proposes the first neuro-symbolic framework. Our method integrates large language model (LLM)-driven RTL rewriting, abstract syntax tree (AST)-based template retrieval-augmented generation (RAG), and fine-grained finite-state machine (FSM) symbolic analysis supporting state merging and partial reduction. It further incorporates formal equivalence checking and test-driven co-verification. This approach transcends the limitations of pattern-matching compilers: on the RTL-Rewriter benchmark, it achieves 43.9% lower power consumption, 62.5% higher performance, and 51.1% smaller area compared to state-of-the-art methods, as validated by Synopsys Design Compiler and Yosys.

Existing RTL synthesis tools (e.g., Yosys) rely solely on control-signal traversal for multiplexer (MUX) tree optimization, making them incapable of detecting and eliminating structural redundancies arising from implicit logical relationships—such as equivalence, implication, or controllability—among input signals. Method: We propose a logic-inference–driven MUX tree optimization framework that first automatically identifies MUX tree topology, then applies Boolean reasoning to uncover equivalence, implication, and don’t-care relationships among inputs, guiding targeted structural simplification and remapping; optimization is evaluated in closed loop using an AIG-area model. Contribution/Results: Evaluated on IWLS-2005 and RISC-V benchmarks, our method reduces average AIG area by 8.95% over Yosys. On million-gate industrial circuits, it achieves a 47.2% improvement in redundant-MUX removal rate, significantly enhancing area efficiency.

This work addresses the challenge of efficiently verifying large-scale RTL designs generated by high-level synthesis (HLS), which often overwhelm conventional model checking techniques. The authors propose a novel method that leverages high-level semantic information from HLS to automatically generate guided invariants, which augment assertions to accelerate formal verification. A proof-guided selection mechanism is introduced to iteratively refine and identify an optimal set of assertions. This approach represents the first systematic integration of HLS-level features into automated invariant generation, substantially improving verification efficiency. Experimental results across multiple HLS benchmarks demonstrate an average speedup of 2.23×, with a maximum acceleration of 6.05× compared to baseline methods.

Large language models (LLMs) face two key challenges in automated IC design: high failure rates in single-shot generation of complex RTL circuits, and poor alignment of conventional chain-of-thought (CoT) reasoning with expert design knowledge and formal verification requirements. Method: We propose VeriBToT, a novel LLM inference paradigm built upon the Backtrack-ToT framework. It integrates three core mechanisms: (1) self-decoupling—decomposing tasks hierarchically by design abstraction; (2) self-verification—embedding formal verification feedback into the reasoning loop; and (3) verifiability-driven tree-of-thought structure—enabling controllable reasoning direction and adjustable step granularity. VeriBToT deeply embeds the Design-for-Verification (DFV) principle into LLM inference, supporting backtracking-based optimization and modular code generation. Contribution/Results: Experiments demonstrate that VeriBToT significantly improves functional correctness and engineering usability of complex Verilog modules, while reducing human intervention frequency and token consumption.

This work addresses the challenges of directly generating RTL code with large language models (LLMs), which often suffer from verification difficulties, limited optimizability, and poor integration with compiler-driven design flows. To overcome these issues, the authors propose the CPPL framework, which introduces a compiler-mediated interface for the first time. By leveraging a Python-based frontend DSL and a JSON-encoded CPPL intermediate representation (IR), the approach reframes LLM-assisted hardware generation as a statically checkable frontend problem. The framework exploits the CIRCT infrastructure to automatically infer bit widths, validate structural correctness, and lower designs to synthesizable Verilog. This ensures generated circuits are type-safe, hierarchically structured, verifiable, and amenable to optimization. Evaluated on the RTLLM benchmark, the method significantly improves functional correctness and, after CIRCT-based optimization, yields synthesized circuits with substantially fewer AIG nodes.

This study addresses the lack of industrial-grade EDA support and limited high-level synthesis for asynchronous circuits by implementing automated synthesis from imperative programs to asynchronous hardware based on the AHIR framework. The proposed methodology employs a delay-insensitive controller coupled with a single-rail datapath architecture. Furthermore, it introduces 1-safe Petri net modeling and formally proves the necessary and sufficient conditions for timing constraints, while maintaining full compatibility with standard ASIC toolchains. As an end-to-end demonstration, the AES encryption algorithm is synthesized, and post-layout simulations validate both the functional correctness and performance metrics of the resulting circuit. This work ultimately provides a comprehensive solution for the automated design of asynchronous circuits.

This work addresses the challenge that large language models (LLMs) often introduce semantic or logical errors when generating hardware RTL code, failing to meet the stringent reliability requirements of chip design. To overcome this limitation, the paper proposes a novel hardware generation framework that integrates LLMs with formal methods, uniquely combining LLM-driven iterative refinement with formal verification. The approach leverages predefined transformation rules to guide the LLM in progressively refining high-level specifications into RTL code that is formally verifiable for correctness. This integration enhances both the interpretability and reliability of the code generation process. Experimental results demonstrate that the method is not only effective but also efficient in producing correct RTL implementations, thereby offering a promising pathway toward trustworthy LLM-assisted hardware design.

This work addresses the heavy reliance on manual modeling and proof effort in formal verification of SystemVerilog RTL designs by proposing the first fully automated framework for translating RTL to Lean 4. The approach introduces a four-layer hierarchical theorem library encompassing combinational logic, sequential updates, single-cycle behaviors, and reachability/invariant properties. It further integrates an LLM-driven proof loop that automatically generates intermediate lemmas, admitting only those formally verified by the Lean kernel into a reusable lemma pool. Evaluated on six designs, the method successfully produced 403 theorems, of which 287 foundational lemmas were automatically reusable, achieving a reuse rate of 80.2%. This significantly enhances the automation and scalability of formal RTL verification.

This work addresses the limitations of existing high-level synthesis (HLS) tools in balancing sequential semantics with fine-grained control over pipeline design, which hinders optimization of power, performance, and area (PPA). The paper proposes a novel HLS approach based on visibility control that preserves a sequential programming model while enabling precise manipulation of pipeline structures and hazard-handling mechanisms through a unified visibility abstraction. This framework encompasses strategies such as stall insertion, bypassing, speculative execution, delayed commit, and register renaming. Experimental results on a RISC-V core, histogram computation, and an AES accelerator demonstrate that the generated pipelines significantly outperform those from state-of-the-art sequential-semantics-preserving HLS tools, achieving PPA metrics close to hand-optimized RTL implementations and enabling efficient design space exploration.

为解决复杂RTL设计中的属性验证问题，本文提出NeuroAbs框架，通过结合LLM辅助分析与符号表示，并采用CEGAR方法迭代优化，有效加速了验证过程。