netlist optimization

This work addresses the insufficient reliability of large language models in low-level operations on SPICE netlists—a limitation often masked by high-level design reasoning. To rigorously evaluate structural fidelity at the netlist level, the authors introduce NetlistBench, the first benchmark dedicated to netlist structural reliability, comprising 24 task categories and 2,342 test cases. It employs a structure-aware, deterministic verifier to assess model performance on parameter identification, connectivity editing, hierarchical manipulation, and equivalence checking. The study innovatively decouples netlist-level reliability from high-level design tasks and introduces long-span composite editing challenges alongside multi-granularity evaluation strategies. Experiments reveal near-perfect accuracy (96%–100%) on simple edits, but substantial performance drops in device insertion (41%–83%) and equivalence judgment (49%–90%). While reasoning augmentation improves weaker models, maintaining structural consistency in long-span edits remains a critical bottleneck.

In logic synthesis, restructuring operations incur high computational overhead; conventional iterative cut enumeration fails in up to 98% of cases, leading to extensive redundant resynthesis. To address this, we propose a machine learning–based pruning optimization: a classifier is introduced to predict and preemptively prune cuts with high failure probability, significantly reducing unnecessary computation. Our method tightly integrates the classifier into the standard logic synthesis flow without modifying the underlying synthesis engine. Experiments on the EPFL benchmarks and ten large industrial circuits demonstrate an average speedup of 3.9× over the latest ABC implementation. The core innovation lies in shifting failure prediction from a posteriori evaluation to a proactive pruning mechanism—breaking the traditional optimization paradigm while preserving both efficiency and toolchain compatibility.

This paper addresses Boolean circuit minimization—reducing circuit size while preserving functional equivalence. We propose the first lightweight subcircuit replacement framework leveraging Boolean function clustering and SAT-based pre-optimization: an optimized circuit library is precomputed; function clustering compresses the search space; and a linear-time subcircuit traversal algorithm is designed, with theoretical proof that only a linear number of candidate subcircuits need be examined to guarantee effective simplification. The method supports both AIG and BENCH formats and achieves simplification within seconds. Experimental evaluation shows a 4% additional area reduction over ABC on AIG circuits, and an average 30% area reduction on the BENCH benchmark suite—substantially outperforming state-of-the-art tools.

Traditional algorithms for dynamically updating node levels in circuit DAGs during logic optimization suffer from a worst-case time complexity of O(|V|²) under local changes, severely limiting scalability for large-scale circuits. Method: This paper proposes the first bounded dynamic level maintenance algorithm, leveraging partial topological order analysis, incremental graph change modeling, and level constraint propagation. Contribution/Results: The approach reduces theoretical complexity to O(|V|Δ log Δ), overcoming the prior unbounded bottleneck. Evaluated on standard benchmark circuits, it achieves a 1074.8× speedup in level maintenance and a 6.4× end-to-end logic optimization acceleration, while preserving PPA (Power, Performance, Area) quality without degradation.

Existing methods for converting SPICE netlists into human-readable schematics lack guarantees of connectivity correctness and suffer from significantly degraded accuracy as circuit complexity increases. This work proposes a deterministic conversion approach based on Sugiyama’s layered graph layout, integrating an embedded pinout database of 5,093 LTspice symbols and a round-trip connectivity verification mechanism. For the first time, this method enables netlist-to-schematic translation with a binary correctness certificate, ensuring network-by-network equivalence between the generated schematic and the original netlist. Implemented as a client-side, single-file, dependency-free architecture, the approach achieves 100% compilation success and connectivity verification pass rates on the Circuits-LTSpice benchmark and demonstrates an 88.4% verification pass rate on Analog Devices’ official dataset of 3,460 circuits.

本文针对电路图示等价性问题，提出了三个难度递增的基准测试，并使用TPTP和SMT-LIB格式进行了一阶编码，生成了相应的测试实例。

This work addresses the high failure rate of natural language–generated hardware descriptions during synthesis or tape-out, often caused by bit-width mismatches, combinational loops, or incomplete logic. It presents the first integration of dependent types and formal proof into a closed-loop hardware generation pipeline, leveraging Lean 4 to construct a verifiable hardware description language that guides large language models to produce type-safe and provably correct circuit code. By exposing design flaws at compile time, the approach achieves a backend implementation success rate of 95–100%, matches hand-written Verilog in simulation pass rates across three major benchmarks, automatically completes functional equivalence verification, and yields up to 35% area reduction and 30% power savings.

This work addresses a critical gap in existing AIG-based technology mapping methods, which neglect the distribution of complementary edges (inverters), leading to a discrepancy in delay estimation between technology-independent optimization and technology-dependent mapping—particularly detrimental to critical paths. To bridge this gap, the authors propose a delay-driven preprocessing technique that leverages self-dual and self-anti-dual Boolean function transformations to redistribute complementary edges prior to mapping, thereby optimizing inverter placement along critical paths. This approach represents the first application of such Boolean transformations to complementary edge redistribution, effectively reconciling the modeling disparity of inverters in the synthesis flow. Evaluated on the EPFL combinational benchmark suite, the method achieves an average delay reduction of 0.49%, with up to 3.86% improvement on the sqrt circuit, all while preserving the original logic functionality and timing characteristics.

This work addresses key challenges in hardware formal verification—namely, the lack of proof reusability in model checking and the manual effort and poor scalability of interactive theorem proving. The paper presents the first Lean 4–based agent-driven verification framework that automatically translates parametric hardware designs and their natural language specifications into executable formal models, leveraging large language model–guided agents to iteratively generate proofs through feedback loops. Its core innovations include introducing proof accumulation and reuse mechanisms to hardware theorem proving for the first time, establishing an agent-oriented benchmark suite, and enabling parameterized verification with strategy-guided reasoning. Experiments demonstrate 100% proof success across 63 tasks, reducing proof iterations by 50%, shortening proof length by 16.3%, and decreasing verification time by 23.2% compared to baseline approaches.

This study addresses the inadequacy of post-layout mapping decisions in accounting for surrounding timing constraints, fanout loads, and interconnect effects. To overcome this limitation, it proposes a local remapping framework that couples discrete search with physical feedback. The approach first isolates timing-critical regions and employs continuous relaxation to prune the search space. It then leverages mixed-integer programming to jointly optimize logic cuts, signal polarities, and library cell selection, modeling delays based on estimated placements. Finally, a closed-loop verification process encompassing legalization, routing parasitic estimation, and timing analysis is conducted to guide subsequent iterative searches. This work thereby achieves precise, physically aware, and timing-driven logic remapping.