microcontroller sensor integration

This work addresses the high instruction overhead and software complexity inherent in traditional soft processors, which rely on explicit instructions to read sensors and generate PWM signals within control loops. The authors propose an innovative architecture that maps high-frequency peripheral inputs directly to general-purpose registers and fully offloads PWM generation to dedicated hardware, thereby enabling zero-instruction sensor access and continuous actuation without software intervention. Implemented on a 32-bit, five-stage pipelined MIPS-style RISC soft core, the design incorporates direct peripheral-to-register-file write ports, a single-cycle multiplier, and hardware-based PWM logic. Experimental results demonstrate a reduction in the control loop cycle count from 91 to 43, eliminating five critical instructions; under a 20 ms control frame, the system achieves a real-time margin of 7,300–15,000×, substantially simplifying software and enhancing computational efficiency.

This work addresses the challenge of end-to-end machine learning inference on microcontroller-class edge devices under stringent constraints on memory, energy consumption, and latency. To bridge the gap between conventional machine learning pipelines and embedded deployment realities, the authors propose a robust design framework tailored for resource-constrained environments, encompassing data acquisition, preprocessing, model compression, and streaming deployment. The framework integrates sampling buffers, feature dimensionality reduction techniques (e.g., RMS, spectral features, MFCCs), validation strategies for class imbalance, and co-optimization of models with runtime systems to form a complete embedded ML pipeline. Experimental evaluations on two representative tasks—inertial human activity recognition and keyword spotting—demonstrate that the proposed approach enables efficient, practical, and robust on-device inference, significantly narrowing the divide between general-purpose machine learning methodologies and embedded implementation requirements.

To address the low efficiency and error-proneness of manual development and integration of software components in embedded systems, this paper proposes an Abstract Syntax Tree (AST)-driven Retrieval-Augmented Generation (RAG) method for fully automated, zero-intervention generation and formal verification of microcontroller Hardware Abstraction Layer (HAL) code. Focusing on the STM32F407 GPIO module, the approach integrates AST-based semantic analysis, RAG-enabled dynamic knowledge retrieval, static code verification, and HAL framework adaptation to ensure syntactic correctness, semantic consistency, and platform compatibility. Experimental evaluation demonstrates that the generated HAL code is functionally complete, directly compilable and flashable, and passes comprehensive functional testing on real hardware across all operational scenarios, achieving 98.7% accuracy. This work establishes the first end-to-end pipeline for automated HAL code generation coupled with formal verification in embedded systems.

This work addresses a critical limitation in existing formal verification tools for open-source hardware PLC programs: the neglect of microcontroller bit-width and sensor ADC resolution, which leads to numerous false positives and missed real defects. To overcome this, the authors propose a hardware-faithful verification approach that employs a declarative Hardware Abstraction Layer (HAL) to precisely model target platform characteristics—such as 16-bit word size, I/O constraints, and ADC resolution—and integrates finite-precision arithmetic with physically realizable input ranges into the formal verification of IEC 61131-3 programs. HAL parameters are automatically derived from official Arduino core definitions and incorporated into the ESBMC ladder logic frontend. Evaluation on 123 real-world programs demonstrates that the method eliminates all 54 false alarms, uncovers genuine bit-width-dependent bugs, and produces reproducible, hardware-realizable counterexamples.

Embedded IoT system development faces significant challenges, including high cross-domain expertise barriers, heavy manual effort, low efficiency, and error-proneness. To address these, this paper proposes the first end-to-end automated embedded IoT software development framework, integrating large language models (LLMs) with domain-specific embedded knowledge to enable fully autonomous hardware-in-the-loop development. Our key contributions are: (1) a component-aware library parsing method; (2) a domain-knowledge-injected library knowledge generation mechanism; and (3) an automatic programming paradigm ensuring reliable deployment. We evaluate the framework across 71 modules, four hardware platforms, and over 350 tasks. Results show a code accuracy of 95.7% and an end-to-end task success rate of 86.5%, outperforming human experts by up to 53.4% in task completion.

This work addresses the inefficiencies and semantic inconsistencies arising from separately implementing driver and monitor programs in traditional hardware module testing. To overcome this, the authors propose a domain-specific language (DSL) tailored to hardware communication protocols, which enables the unified specification of both driver and monitor logic through an imperative syntax, thereby ensuring their semantic consistency for the first time. Building upon this DSL, they develop a prototype tool that leverages waveform parsing and transaction-level trace inference techniques to accurately reconstruct protocol-compliant transaction sequences from raw signal waveforms. Experimental results demonstrate that the approach significantly improves development efficiency, with further validation planned on real-world interconnect protocols such as Wishbone and AXI-Stream.

This study systematically evaluates whether Rust can compete with C in performance and resource efficiency for microcontroller firmware development and assesses its industrial viability. Two teams independently implemented identical industrial IoT firmware—one in Rust and the other in C—and key metrics including development effort, memory footprint, and execution speed were compared on real hardware. This work presents the first systematic comparison of the two languages in a genuine industrial context and introduces Ariel OS, a lightweight Rust-based runtime. Empirical results demonstrate that Rust matches or exceeds C in both resource utilization and execution performance, while Ariel OS exhibits a smaller binary footprint, collectively establishing Rust as a reliable and competitive choice for microcontroller firmware development.

This work addresses the challenge that existing AI methods struggle to jointly model the tight coupling between software logic and physical hardware behavior in hardware-in-the-loop (HIL) development of embedded and IoT systems, often leading to deployment failures. To tackle this, the authors propose a skill-oriented agent architecture tailored for HIL scenarios and introduce IoT-SkillsBench, a novel real-hardware evaluation benchmark. The framework systematically assesses AI agents across multiple platforms, peripherals, and task complexities through three agent configurations enhanced by skill augmentation, structured expert knowledge injection, and real-hardware validation. Experimental results demonstrate that, over 378 real-world deployments, agents equipped with human-expert-derived skills achieve near-perfect cross-platform task success rates, substantially outperforming baseline approaches.

This work proposes a personalized prototyping platform for circuit development to address the limitations of traditional tutorial-based approaches, which rely on rigid, fixed-step instructions that fail to accommodate makers’ individualized building and debugging practices. Central to the platform is a circuit-aware enhanced breadboard integrated with hardware-in-the-loop reconfiguration, context-aware guidance algorithms, and in-situ interactive testing techniques. This integration enables, for the first time, nonlinear, real-time, hardware-context-driven guidance and circuit validation. A user study (N=12) demonstrates that the system effectively aligns with users’ unique construction and troubleshooting behaviors, significantly improving both prototyping efficiency and user experience.